1. Field of the Invention
The present invention relates to non-volatile memory devices and, more particularly, to localized trapped charge memory cell structures capable of storing multiple bits per cell.
2. Description of Related Art
A non-volatile semiconductor memory device is designed to maintain programmed information even in the absence of electrical power. Read only memory (ROM) is a non-volatile memory commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices such as cellular phones.
ROM devices typically include multiple memory cell arrays. Each memory cell array may be visualized as including intersecting word lines and bit lines. Each word and bit line intersection can correspond to one bit of memory. In mask programmable metal oxide semiconductor (MOS) ROM devices, the presence or absence of a MOS transistor at word and bit line intersections distinguishes between a stored logic ‘0’ and logic ‘1’. A programmable read only memory (PROM) is similar to the mask programmable ROM except that a user may store data values (i.e., program the PROM) using a PROM programmer. A PROM device is typically manufactured with fusible links at all word and bit line intersections. This corresponds to having all bits at a particular logic value, typically logic ‘1’. The PROM programmer is used to set desired bits to the opposite logic value, typically by applying a high voltage that vaporizes the fusible links corresponding to the desired bits. A typical PROM device can only be programmed once.
An erasable programmable read only memory (EPROM) is programmable like a PROM, but can also be erased (e.g., to an all logic ‘1’s state) by exposing it to ultraviolet light. A typical EPROM device has a floating gate MOS transistor at all word and bit line intersections (i.e., at every bit location). Each MOS transistor has two gates: a floating gate and a non-floating gate. The floating gate is not electrically connected to any conductor, and is surrounded by a high impedance insulating material. To program the EPROM device, a high voltage is applied to the non-floating gate at each bit location where a logic value (e.g., a logic ‘0’) is to be stored. This causes a breakdown in the insulating material and allows a negative charge to accumulate on the floating gate. When the high voltage is removed, the negative charge remains on the floating gate. During subsequent read operations, the negative charge prevents the MOS transistor from forming a low resistance channel between a drain terminal and a source terminal (i.e., from turning on) when the transistor is selected.
An EPROM integrated circuit is normally housed in a package having a quartz lid, and the EPROM is erased by exposing the EPROM integrated circuit to ultraviolet light passed through the quartz lid. The insulating material surrounding the floating gates becomes slightly conductive when exposed to the ultraviolet light, allowing the accumulated negative charges on the floating gates to dissipate.
A typical electrically erasable programmable read only memory (EEPROM) device is similar to an EPROM device except that individual stored bits may be erased electrically. The floating gates in the EEPROM device are surrounded by a much thinner insulating layer, and accumulated negative charges on the floating gates can be dissipated by applying a voltage having a polarity opposite that of the programming voltage to the non-floating gates.
Flash memory devices are sometimes called flash EEPROM devices, and differ from EEPROM devices in that electrical erasure involves large sections of, or the entire contents of, a flash memory device.
A relatively recent development in non-volatile memory is localized trapped charge devices. While these devices are commonly referred to as nitride read only memory (NROM) devices, the acronym “NROM” is a part of a combination trademark of Saifun Semiconductors Ltd. (Netanya, Israel). Each memory cell of a localized trapped charge array is typically an n-channel MOS (nMOS) transistor with an oxide-nitride-oxide (ONO) dielectric structure forming the gate dielectric. Data is stored in two separate locations adjacent to the source and drain terminals of the nMOS transistor, allowing 2 bits of data to be stored in the nMOS transistor structure. The localized trapped charge memory cells are typically programmed by channel hot electron (CHE) injection through bottom oxide layers of the ONO dielectric structures. During programming, electrical charge is trapped in the ONO dielectric structures. The localized trapped charge memory cells are erased by tunneling enhanced hot hole (TEHH) injection through bottom oxide layers of the ONO dielectric structures.
Materials formed on and/or positioned in semiconductor substrates in the manufacture of integrated circuits are subject to physical and chemical mechanisms influenced by thermal (heat) energy. More specifically, heat energy may accelerate physical and chemical mechanisms deleterious to proper operation of the integrated circuits. For this reason, “thermal budgets” are determined for semiconductor wafer fabrication processes. These thermal budgets specify maximum total quantities of thermal energy to which wafers can be subjected, and wafer processing is generally carried out such that specified thermal budgets are not exceeded.
In a known method for forming localized trapped charge memory cell structures, dopant atoms (e.g., phosphorus atoms) are introduced into substrates to form buried source/drain regions of nMOS transistor structures. These source/drain regions function as bit lines of the memory cells. Relatively thick oxide layers are grown over the buried source/drain regions to electrically isolate the buried source/drain regions from word lines subsequently formed over the oxide layers.
A problem arises in the known method in that growing the relatively thick oxide layers typically requires subjecting the substrates to relatively high temperatures for relatively long periods of time. The amount of thermal energy the substrate is subjected to during the oxide growth process may account for a substantial portion of, or even exceed, a thermal budget for the process determined at least in part by the tendency of the dopant atoms in the previously formed source/drain regions to migrate (i.e., diffuse) under elevated temperatures.
It would thus be advantageous to have a localized trapped charge memory cell structure wherein electrical isolation between word and bit lines is provided by layers of a material that can be formed using less thermal energy than an oxide growth process.